1. Novel Neuromorphic Semiconductor Devices (Synaptic Transistor, Trancitor)
Having a limitation of the existing computer architecture and semiconductor technologies, a brain-inspired system is getting an intensive attention for a high speed and low power electronic system, e.g. computers. One of the key elementary parts of the brain is the Synapse, and many research groups have been trying to emulate it in a form of electronic devices, called Synaptic Transistor, where a flash memory structure or Memristor is employed. Since this kind of approach shows a limitation in terms of performance (a high power consumption), large physical size and macro-functionality, the LEE lab (our group) is trying to develop a novel Synaptic device which is more resemble with a human brain’s, and a more microscopic form of devices, e.g. Synaptic Pass-Transistors (SPT). Here, we are also trying to incorporate our proposed device, called “Trancitor” as well.
* Related Projects:
- Low Power Synaptic Device Design and Optimization (funded by Samsung).
- Ultra-Low Power Synaptic Thin-Film Devices (기초연구실 지원사업 – BRL – 과학기술정보통신부, NRF)
* Representative paper:
- Sungsik Lee, “A Missing Active Device—Trancitor for a New Paradigm ofElectronics,” IEEE Access, vol.6, pp. 46962-46967, 23 August 2018 (arXiv, MIT Tech Review, YouTube, IEEE Access).
- Y. Kang, J. Jang, D. Cha, and Sungsik Lee*, “Synaptic Weight Evolution and Charge Trapping Mechanisms in a Synaptic Pass-Transistor with a Direct Potential Output,” IEEE Transactions on Neural Networks and Learining Systems (TNNLS), 2021 (published online as early access, *Corresponding author):
2. Ultra Low Energy Electronics and Devices (MOSFET, TFT)
We would like to develop a new form of transistor that which can drastically reduce the power consumption, being based on thin-film technologies, e.g. organics and inorganics. As an example reported in the journal Science, we can use a tiny leakage current conduction in a field effect transistor which is virtually switched off, i.e. in the deep sub-threshold regime – we are calling it ‘Almost-off transistors’. This operational regime is reminiscent of a computer in sleep-mode but which remains active in processing information. To demonstrate the idea, we can employ a thin film transistor based on a semiconducting oxide material (in this case, In-Ga-Zn-O) with a Schottky barrier at the current terminals. Due to the wide energy band-gap of the oxide material, the transistor’s off current was extremely low. Consequently, the transistor’s operating voltage is less than a volt with power consumption below a nanowatt. The beauty of the device lies in its high intrinsic gain (in excess of 400) and infinite output resistance, thanks to the input-output isolation by Schottky barriers created by design. It circumvents the previously unresolved problem of low-temperature processed thin film transistors, i.e. the short channel effect associated with inevitably thick gate insulator and restriction on a gate voltage. These characteristics remain independent of transistor geometry and operating voltage. This family of transistors can be layered on a broad range of substrates ranging from glass and plastic to polyester and paper using low-temperature processes. Oxide materials have already demonstrated their potential in transparent displays, and are a promising candidate for other low cost and large area electronic applications. Because of the ultra-low bias current (< 2pA), a typical battery with 2000 mA-hr specification would have an infinite lifetime (> 0.1 billion years), and thus there is no need to replace or recharge it. Regarding this area, our research and project scope also covers all aspects of emerging semiconductor technology to minimise power consumption from the levels of materials to devices for circuit design:
- Device categories:
- Unipolar device: Field-effect transistors, e.g. MOSFET / MISFET
- Large area electonic device: Thin-film transistor (TFT)
- Low cost TFT for non-display applications, analog and digital circuits for wearable sensors in IoT
- Process technologies and Materials selections:
- Innovative process for dielectrics, semiconducting layers, metal interconnections, etc.
- Band-gap engineering, defect control, work-function engineering, etc.
- Device concepts and architectures:
- Threshold voltage engineering, sub-threshold slope engineering (e.g. tunnelling barriers), etc.
- Schottky vs. ohmic contact devices, etc.
- Sub-threshold operation for ultra low power and high gain, etc.
3. Multi-functional Wearable Systems
For example, to be a high optical sensitivity, a heterojunction oxide channel can be incorporated into thin-film transistor (TFT) structure. One of these layers should be thin and oxygen deficient, like ZnO and InZnO with a high density of oxygen defects (DO), e.g. oxygen vacancies and interstitials, for high optical absorption due to optical ionisation of the oxygen defects, called persistent photoconductivity (PPC). Here, we can think of a bilayer structure where visible light absorption and charge separation are happening, for example, in In-Ga-Zn-O/In-Zn-O (i.e. IGZO/IZO) bi-layer channel TFTs. The other layer is relatively thick and compensated with, e.g. Ga or Hf, thus containing less amount of oxygen defects, hence making them less conductive. The layers in the heterostructure provide a valence band offset, giving rise to effective charge separation for high quantum efficiency. However, as an optimisation issue, the thickness of the light absorption layer should be optimised to get a positive threshold voltage for enhancement mode operation. Although there is visible light absorption, transparency is maintained at higher wavelengths, thus suited for transparent image capture. This kind of research can also lead to a transparent optical memory besides photo-sensors, thus multifunctionality.
* Representative paper: Sungsik Lee, Sanghun Jeon, Reza Chaji, and Arokia Nathan, “Transparent Semiconducting Oxide Technology for Touch Free Interactive Flexible Displays,” Proceedings of the IEEE 103, 664 (2015).
4. Semiconductor Physics and Device Modeling
A TFT compact model needs to be developed that allow expedient simulation of analog and digital circuits for the design of an all integrated system along the lines discussed in the next Section. The models have to be physically based so as to minimise the number of fitting coefficients and simple device parameter extraction. As we know, oxide TFTs, e.g. IGZO TFTs, can exhibit a high mobility even when fabricated at room temperature. This is mainly due to ionic bonding structure which is insensitive to bonding angle disorder. However, this class of channel materials has a compositional disorder. This makes a potential barrier above the conduction band minima (Em), suggesting percolation conduction when electrons are released into the conduction band. Moreover, there are localized tail states within the gap states, implying trap-limited conduction (TLC). In particular, the oxide semiconductor has a shallow slope of the tail states (kTt) ~ 20meV, smaller than the thermal energy (kT) at 300K, leading to different mobility behaviour.
Based on percolation and trap-limited conduction, the field effect mobility model needs to be modeled. For the large signal and small signal behaviours, we incorporated resistors and capacitors into an equivalent model for TFTs. Here, a RC product can explain a channel formation time. So far, this has been used in an empirical way. However, this approach fails to express ‘Non-Quasi-Static (NQS) dynamic behaviour’ while it is enough to reproduce a ‘Quasi-Static (QS) dynamic behaviour’. At the same time, it is not able to capture physical/geometrical mechanisms (e.g. trapping on localised traps and related channel-length dependent channel formations) and temperature dependency on Quasi-Static dynamic behaviour either. So, it is now required to develop a fully physically-based dynamic model for oxide TFTs while addressing both NQS and QS behaviours. If we got this, it would be breakthrough in this area. So, I would like to make this breakthrough.
* Representative paper: Sungsik Lee and Arokia Nathan, “Conduction Threshold in Accumulation-Mode InGaZnO Thin Film Transistors,” Scientific Reports 6, 22567 (2016).